1. Field of the Invention
The invention relates in general to a chip package structure and a wafer structure for manufacturing the chip package structure, and more particularly to a stacked structure of chips, and a wafer structure for manufacturing the stacked structure of chips.
2. Description of the Related Art
Living in the age of information, users are in pursuit of high-speed, high-quality and multi-functional electronic products. In terms of the appearances of electronic products, the design is directed towards the trends of light-weight, slimness and compactness. To achieve the above objects, many manufacturers introduce the concept of systematization in circuit design for integrating several functions into one single chip such that the required number of chips in an electronic product is reduced. In order to co-operate with the trends of light-weight, slimness and compactness in the design of appearances, many new concepts in package technology are developed. Examples of the new concepts in package design include multi-chip module (MCM) package design, chip scale package (CSP) package design, and stacked structure of chips package design.
FIG. 1 is a cross-sectional view of a conventional stacked structure of chips. Referring to FIG. 1, the conventional stacked structure of chips 100 includes a plurality of stacked chip packages 200a and 200b and a plurality of solder balls 250, wherein the chip packages 200a attached to the chip package 200b are fixed on the chip package 200b by many solder balls 250, and are electrically connected to the chip package 200b via the solder balls 250. Each of the chip packages 200a and 200b includes a package carrier 210, a chip 220, a plurality of bumps 230 and an underfill 240. The chip 220 and the bumps 230 are disposed on the package carrier 210, and the chip 220 is electrically connected to the package carrier 210 via the bumps 230. The underfill 240 is disposed between the chip 220 and the package carrier 210 for wrapping the bumps 230 and mitigating the thermal stress between the chip 220 and the package carrier 210.
The package carrier 210 has a plurality of conductive elements 212 and a plurality of solder pads 214, wherein the conductive elements 212 respectively pass through the package carrier 210, and the solder pads 214 are respectively disposed on the conductive elements 212. Besides, the solder balls 250 are respectively disposed between the solder pads 214 of the chip package 200a and the solder pads 214 of the chip package 200b. Thus, the chip packages 200a and 200b are electrically connected together via the solder balls 250.
As both the package carriers 210 and chip 220 have a certain thickness and both the bumps 230 and the solder balls 250 have a certain height, the chip package 200a and 200b will have a certain thickness which is hard to be reduced. When a plurality of chip packages (200a, 200b. . . ) are stacked to form a stacked structure of chips 100, the thickness of the stacked structure of chips 100 will increase sharply and become unfavorable in terms of design. Therefore, under the restrictions of maintaining the volume and the thickness at a fixed level, the package integration of the stacked structure of chips 100 is hard to improve.